Interconnect Technique for Tight Clearance in Stacked-die Package

The paper focused in addressing wire-related assembly issues due to tight clearances in the semiconductor package design. Package design characterization was done considering the assembly design rules and the advanced rules, resulting to the integration of an interposer in the package design. With the new design, the assembly limitations and capability could be improved specifically for semiconductor devices with tight clearance requirement. Furthermore, gross assembly rejections related to tight clearances could be mitigated with the design solution and process improvement.